As is known, to read the cells of nonvolatile, particularly flash, memories, the row and column to which the cell to be read is connected are appropriately biased and the current flow through the cell is detected. If the cell is written, its threshold voltage is higher than the read voltage and the cell conducts no current. If the cell is erased, its threshold voltage is lower than the read voltage, and the cell conducts current. Written and erased cells are discriminated by comparing the current flow in the cell with a reference current generated by a reference cell. The comparison is made by a read circuit comprising a current/voltage converter for converting the current of the cell to be read and the reference cell into corresponding voltages, and comprising a sense amplifier for comparing the two voltages and generating a logic output signal, the state of which depends on the outcome of the comparison.
To ensure correct read operation and reliable cycling (multiple cycle operation) of the memory array, certain limits must be posed on the distribution of the threshold voltages of the cells. More specifically, currently used technologies require that the threshold voltage of the most erased cells be above zero, and the threshold voltage of the worst erased cells be about 2.5 V. The lower limit substantially arises from the need to ensure against read errors caused by depleted cells (cells with a threshold voltage below zero), while the upper limit is due to the intrinsic distribution of the cell threshold voltages according to the fabrication technology used.
Since the read voltage normally coincides with the supply voltage, read problems arise in the case of a low supply voltage (about 2.5 V), due to the poorly erased cells, which conduct a very low current, being considered written and so resulting in read errors.
In view of the current demand for memories capable of operating within a wide range in relation to the supply voltage (typically, with supply voltages of 2.5 to 4 V) and with fast access times (&lt;100 ns), a sense amplifier is required, which is capable of fast, correct reading within the fall range of supply voltages involved.
To solve the problem of achieving a reasonable read time of poorly erased cells, a co-pending patent application, entitled "Method and circuit for reading low-supply-voltage memory array cells" (Attorney Docket No. 854063.453), filed Jun. 18, 1997, relates to a solution in which the current/voltage converter operates in the opposite way as compared with standard converters, to enable even poorly erased array cells to be read rapidly in the presence of low supply voltage (when the memory cells conduct a low current).
For the written cells to be determined correctly, however, the above solution poses limits as regards the maximum permissible supply voltage.
To give a clearer idea of the problem, FIGS. 1 and 2 show the solution proposed in the above co-pending patent application.
In FIG. 1, the read circuit is indicated by 1, and comprises an array branch 2 and a reference branch 3. Array branch 2 comprises an array cell 4 to be read, forming part of a memory array 5 and connected to an array bit line 6 and reference branch 3 comprises a reference cell 7 connected to a reference bit line 8. Array bit line 6 (together with other array bit lines not shown and forming part of memory array 5) and reference bit line 8 are connected to a current/voltage converter 9 via a conventional decoding, biasing and equalizing circuit 10 not essential to the description and therefore not shown in detail. Circuit 10 provides for selecting the array bit line 6 of the cell 4 to be read, appropriately biasing it (and reference bit line 8) to prevent spurious read phenomena such as soft writing, and possibly also equalizing lines 6 and 8 before the cell is actually read.
Converter 9 comprises an array load 12 and reference load 13 forming a current mirror circuit and connected to array and reference bit lines 6 and 8 via circuit 10. More specifically, and according to the teachings of the above co-pending patent application, array load 12 comprises a diode-connected PMOS transistor, and reference load 13 a PMOS transistor. Array load transistor 12 has the source terminal connected to a supply line 15 at V.sub.CC, the drain terminal connected to circuit 10 at a node 16, the gate terminal connected to the gate terminal of reference load transistor 13, and a width/length ratio W/L=K. And reference load transistor 13 has the source terminal connected to supply line 15, the drain terminal connected to circuit 10 at a node 17, and a width/length ratio W/L=N*K, where N is a multiplication constant.
Nodes 16, 17 are connected to the inputs of sense amplifier 18.
In the FIG. 1 circuit, since the diode (low-impedance) element is connected to array bit line 6 instead of to reference bit line 8, and in view of the width/length ratio of transistors 12 and 13, the current in I/V converter 9 is imposed by memory cell 4, and is supplied, amplified by N, to reference branch 3 where it is compared with the current flowing in reference cell 7. This therefore provides for rapidly reading the array cell, even when it is poorly erased and conducts only a small amount of current due to the low supply voltage.
FIG. 2 shows the current/voltage characteristics obtainable from the FIG. 1 circuit by biasing the drain terminal of the cells (both array and reference cells) at about 1 V (linear operating region) and assuming a boost voltage V.sub.B is used to increase the voltage V.sub.GS between the gate and source terminals of cell 4 with respect to supply voltage V.sub.CC.
In FIG. 2, I.sub.R indicates the I/V characteristic of the reference cell with a fixed, known threshold voltage V.sub.TR. I.sub.TC indicates the characteristic of the worst erased array cell with the maximum permissible threshold voltage V.sub.TC (2.5 V with the above specifications); I.sub.TCN indicates characteristic I.sub.TC amplified by the FIG. 1 configuration. I.sub.TCNB indicates characteristic I.sub.TCN in the presence of bootstrap voltage V.sub.B --by which it is shifted by V.sub.B towards the origin--and therefore presenting a threshold voltage of (V.sub.TC -V.sub.B). I.sub.TW indicates the characteristic of the worst written array cell with the minimum permissible threshold voltage V.sub.TW. I.sub.TWN indicates characteristic I.sub.TW amplified by the FIG. 1 configuration. And I.sub.TWNB indicates characteristic I.sub.TWN in the presence of bootstrap voltage and with a threshold voltage of (V.sub.TW -V.sub.B).
As shown clearly in FIG. 2, the intersection of characteristics I.sub.R and I.sub.TCNB determines the minimum supply voltage V.sub.1, and that of characteristics I.sub.R and I.sub.TWNB the maximum supply voltage V.sub.2, i.e., the voltages below and above which reading (recognition of erased and written cells respectively) is not possible.
Voltages V.sub.1 and V.sub.2 may be determined analytically, bearing in mind that: EQU I.sub.R =G*(V-V.sub.TR) (1) EQU I.sub.TC =G*(V-V.sub.TC) EQU I.sub.TCN =N*I.sub.TC =N*G*(V-V.sub.TC) EQU I.sub.TW =G*(V-V.sub.TW) EQU I.sub.TWN =N*I.sub.TW =N*G*(V-V.sub.TW) EQU I.sub.TCNB =N*G*(V-V.sub.TC +V.sub.B) (2) EQU I.sub.TWNB =N*G*(V-.sub.VTW +V.sub.B) (3)
where G is the slope of the nonamplified characteristics.
By equaling relation (1) to (2) and relation (1) to (3), the following voltages are obtained: EQU V.sub.1 =(N*V.sub.TC -N*V.sub.B -V.sub.TR)/(N-1) EQU V.sub.2 =(N*V.sub.TW -N*V.sub.B -V.sub.TR)/(N-1)
For example, if V.sub.TC =2.5 V, V.sub.TW =4.5 V, V.sub.TR =1.25 V, V.sub.B =0.8 V and N=8, then V.sub.1 =1.76 V and V.sub.2 =4 V.
As such, though the above solution provides for reading memory cells even when the minimum supply voltage is low, the maximum permissible supply voltage is also low.
For also reading memory cells with a high maximum supply voltage, but without at the same time increasing the minimum supply voltage, according to a further co-pending patent application entitled "Method and circuit for generating a read reference signal for nonvolatile memory cells" (Attorney Docket No. 854063.455), filed Jun. 18, 1997 and incorporated herein by way of reference, the reference characteristic comprises two segments with different slopes.
In read circuits of the type considered, to speed up reading in the presence of a low supply voltage, an equalizing network is used to connect nodes 16 and 17 and bring them to the same voltage before they are read. Since it depends, however, on various parameters, and in view of the unbalanced loads involved, the actual voltage level reached by nodes 16 and 17 cannot be established accurately beforehand, and, in the event of an unbalanced voltage level, reading may be commenced erroneously before eventually reaching the correct value, thus resulting in such a time loss as to at least partly reduce the theoretic advantage of the equalizing function.